Modeling of Ultrathin Double-Gate nMOS/SOI Transistors

IEEE Transactions on Electron Devices

Volumn 41, Issue 5, 1994, Pages 715-720

  Flandre, Denis ^b   Terao, Akira ^a   Wiele, Fern ^a  

^a UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

^b National Fund for Scientific Research   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION THEORY; CHARGE CARRIERS; ELECTRONS; GATES (TRANSISTOR); IMPURITIES; MOS DEVICES; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY; THIN FILMS;

GATE ALL AROUND TECHNOLOGY; POISSON EQUATION; THRESHOLD SURFACE POTENTIAL; THRESHOLD VOLTAGE; ULTRATHIN DOUBLE GATE N-CHANNEL STRUCTURE; WEAK INVERSION MECHANISM;

SEMICONDUCTOR DEVICE MODELS;

EID: 0028427763     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.285022     Document Type: Article

References (15)

1. J.-P. Colinge, M. H. Gao, A. Romano-Rodriguez, H. Maes, and C. Claeys, “Silicon-on-insulator gate-all-around device,” IEDM Tech. Dig., p. 595, 1990.
2. F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, “Double-gate silicon-on-insulator transistor with volume inversion: a new device with greatly enhanced performance,” IEEE Electron Device Lett., vol. 8, pp. 410–412, 1987.
3. D. Hisamoto, T. Kaga, Y. Kawamoto, and E. Takeda, “A fully depleted lean-channel transistor (DELTA),” IEDM Tech. Dig., pp. 833–836, 1989.
4. H. Horie et al., “Fabrication of double gate thin film SOI MOSFETs using wafer bonding and polishing,” Int. Solid State Devices and Materials Conf., 1991, Yokohama, Japan.
5. A. Terao and F. Van de Wiele, “An analytical model for GAA transistors,” Proc. ESSDERC’91, Microelectronic Engineering, vol. 15, pp. 233–236, 1991.
6. M. Schubert, B. Höfflinger, and R. P. Zingg, “An analytical model for strongly inverted and accumulated silicon films,” Solid-State Electronics, vol. 33, no. 12, pp. 1553–1568, 1990.
7. M. Schubert and B. Höfflinger, “A one-dimensional analytical model for the dual-gate-controlled thin-film SOI MOSFET,” IEEE Electron Device Lett., vol. 12, pp. 489–491, 1991.
8. A. Ortiz-Conde, F. J. Garcia Sanchez, P. E. Schmidt, and A. Sa-Neto, “The foundation of a charge-sheet model for the thin-film MOSFET,” Solid-State Electronics, vol. 31, pp. 1497–1500, 1988.
9. J. B. McKitterick and A. L. Caviglia, “An analytical model for thin SOI transistors,” IEEE Trans. Electron Devices, vol. 36, pp. 1133–1138, 1989.
10. B. Mazhari, S. Cristoloveanu, D. E. Ioannou, and A. L. Caviglia, “Properties of ultra-thin wafer-bonded silicon-on-insulator MOSFET’s,” IEEE Trans. Electron Devices, vol. 38, pp. 1289–1295, 1991.
11. F. Balestra, G. Ghibaudo, M. Benachir, and J. Brini, “Modeling of single and double gate thin film SOI MOSFET’s,” Proc. ESSDERC’89, Berlin, Germany, pp. 889–892, 1989.
12. P. Francis, A. Terao, D. Flandre, and F. Van de Wiele, “Characteristics of nMOS/GAA (Gate-All-Around) transistors near threshold,” Proc. ESSDERC’92, Microelectronic Engineering, vol. 19, pp. 815–818, 1992.
13. H.-S. Wong, M. H. White, T. J. Krutsick, and R. V. Booth, “Modeling of transconductance degradation and extraction of threshold voltage in thin oxide MOSFET’s,” Solid-State Electronics, vol. 30, no. 9, pp. 953–968, 1987.
14. J.-P. Colinge, Silicon-on Insulator Technology: Materials to VLSI. Amsterdam: Kluwer, p. 116, 1991.
15. D. J. Wouters, J.-P. Colinge, and H. E. Maes, “Subthreshold slope in thin-film SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 37, pp. 2022–2033, 1990.