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1
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0004286686
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Modern Power Devices
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B. J. Baliga, Modern Power Devices. New York: Wiley, 1987.
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(1987)
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Baliga, B.J.1
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3
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0023330527
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An ultralow on-resistance power MOSFET fabricated by using a fully self-aligned process
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D. Ueda, H. Takagi, and G. Kano, “An ultralow on-resistance power MOSFET fabricated by using a fully self-aligned process,” IEEE Trans. Electron Devices, vol. ED-34, pp. 926–930, 1987.
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(1987)
IEEE Trans. Electron Devices
, vol.ED-34
, pp. 926-930
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Ueda, D.1
Takagi, H.2
Kano, G.3
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4
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84895223636
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Self-aligned UMOSFET's with a specific on-resistance of 1 mΩ. cm2
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H.-R. Chang, R. D. Black, V. A. K. Temple, W. Tantraporn, and B. J. Baliga, “Self-aligned UMOSFET's with a specific on-resistance of 1 mΩ. cm2,” IEEE Trans. Electron Devices, vol. ED-34, pp. 2329–2334, 1987.
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(1987)
IEEE Trans. Electron Devices
, vol.ED-34
, pp. 2329-2334
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Chang, H.-R.1
Blackx, R.D.2
Temple, V.A.K.3
Tantraporn, W.4
Baliga, B.J.5
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5
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0024124571
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TDMOS-An ultralow on-resistance power transistor
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S. Mukherjee, M. Kim, L. Tsou, and M. Simpson, “TDMOS-An ultralow on-resistance power transistor,” IEEE Trans. Electron Devices, vol. ED-35, pp. 2459, 1988.
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(1988)
IEEE Trans. Electron Devices
, vol.ED-35
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Mukherjee, S.1
Kim, M.2
Tsou, L.3
Simpson, M.4
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6
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0024629947
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Numerical and experimental comparison of 60 V vertical double-diffused MOSFETs and MOSFETs with a trench-gate structure
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H.-R. Chang, “Numerical and experimental comparison of 60 V vertical double-diffused MOSFETs and MOSFETs with a trench-gate structure,” Solid-State Electronics, vol. 32, pp. 247–251, 1989.
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(1989)
Solid-State Electronics
, vol.32
, pp. 247-251
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Chang, H.-R.1
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8
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0026158322
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Trench DMOS transistor technology for high-current (100 A range) switching
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C. Bulucea and R. Rossen, “Trench DMOS transistor technology for high-current (100 A range) switching,” Solid State Electronics, vol. 34, pp. 493–507, 1991.
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(1991)
Solid State Electronics
, vol.34
, pp. 493-507
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Bulucea, C.1
Rossen, R.2
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9
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0026202239
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Ultralow specific on resistance UMOSFET with trench contacts for source and body regions realized by selfaligned process
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S. Matsumoto, T. Ohno, and K. Izumi, “Ultralow specific on resistance UMOSFET with trench contacts for source and body regions realized by selfaligned process,” Electron. Lett., vol. 27, pp. 1640–1642, 1991.
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(1991)
Electron. Lett.
, vol.27
, pp. 1640-1642
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Matsumoto, S.1
Ohno, T.2
Izumi, K.3
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10
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0004418847
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A study on a high blocking voltage UMOS-FET with a double gate structure
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& ICs, Tokyo
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Y. Baba, N. Matsuda, S. Yanagiya, S. Hiraki, and S. Yasuda, “A study on a high blocking voltage UMOS-FET with a double gate structure,” pp. 300–302, in Proc. 1992 Int. Symp. Power Semiconductor Device & ICs, Tokyo, 1992.
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(1992)
Proc. 1992 Int. Symp. Power Semiconductor Device
, pp. 300-302
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Baba, Y.1
Matsuda, N.2
Yanagiya, S.3
Hiraki, S.4
Yasuda, S.5
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11
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0024718325
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Characteristics of trench j-MOS power transistors
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B. A. Maclver, S. J. Valeri, K. C. Jain, J. C. Erskine, and R. Rossen, “Characteristics of trench j-MOS power transistors,” IEEE Electron Device Lett., vol. 10, pp. 380–82, 1989.
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(1989)
IEEE Electron Device Lett.
, vol.10
, pp. 80-82
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Maclver, B.A.1
Valeri, S.J.2
Jain, K.C.3
Erskine, J.C.4
Rossen, R.5
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12
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84946244439
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Two-dimensional device analysis program
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TMA PISCES-2B Version 9033
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TMA PISCES-2B, “Two-dimensional device analysis program,” Version 9033, 1990, Technology Modeling Associates, Inc.
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(1990)
Technology Modeling Associates, Inc
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13
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0026238437
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Reactive ion etching of silicon trenches using SF6/O2gas mixtures, J. Electrochem. Soc., vol. 138, pp. 3076–3081, 1991
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T. Syau, B. J. Baliga, and R. W. Hamaker, “Reactive ion etching of silicon trenches using SF6/O2gas mixtures, J. Electrochem. Soc., vol. 138, pp. 3076–3081, 1991.
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(1991)
, vol.138
, pp. 3076-3081
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Syau, T.1
Baliga, B.J.2
Hamaker, R.W.3
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14
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84946243801
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Mobility study on RIE etched silicon surfaces using sf6/o2 gas etchants
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T. Syau and B. J. Baliga, “Mobility study on RIE etched silicon surfaces using sf6/o2 gas etchants,” submitted for publication, 1992.
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(1992)
submitted for publication
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Syau, T.1
Baliga, B.J.2
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15
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0026908575
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The accumulation mode field-effect transistor: A new ultralow on-resistance MOSFET
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B. J. Baliga, T. Syau, and P. Venkatraman, “The accumulation mode field-effect transistor: A new ultralow on-resistance MOSFET,” IEEE Electron Device Lett., vol. 13, pp. 427–429, 1992.
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(1992)
IEEE Electron Device Lett.
, vol.13
, pp. 427-429
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Baliga, B.J.1
Syau, T.2
Venkatraman, P.3
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