A High-Performance Self-Aligned UMOSFET With a Vertical Trench Contact Structure

IEEE Transactions on Electron Devices

Volumn 41, Issue 5, 1994, Pages 814-818

  Yoshino, Hideo ^a   Ishii, Hiromu ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; CAPACITANCE; ELECTRIC CONTACTS; ELECTRIC CURRENTS; ELECTRIC PROPERTIES; ELECTRIC RESISTANCE; GATES (TRANSISTOR); SEMICONDUCTOR DEVICE STRUCTURES;

CRITICAL AVALANCHE CURRENT; HIGH PERFORMANCE SELF ALIGNED UMOSFET; OPTIMUM CELL PITCH; SOURCE CONTACT RESISTANCE; VERTICAL TRENCH CONTACT STRUCTURE;

MOSFET DEVICES;

EID: 0028426036     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.285036     Document Type: Article

References (11)

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