A Portable Parallel Algorithm for Logic Synthesis Using Transduction

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 13, Issue 5, 1994, Pages 566-580

  De, Kaushik ^a   Ramkumar, Ballkrishna ^b   Banerjee, Prithviraj ^c  

^a AGERE SYSTEMS   (United States)

^b UNIVERSITY OF IOWA   (United States)

^c UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; LOGIC CIRCUITS; PARALLEL PROCESSING SYSTEMS;

COMBINATORIAL LOGIC; LOGIC SYNTHESIS; TRANSDUCTION;

VLSI CIRCUITS;

EID: 0028425277     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.277630     Document Type: Article

References (22)

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