A 16-Mb Flash EEPROM with a New Self-Data-Refresh Scheme for a Sector Erase Operation

IEEE Journal of Solid-State Circuits

Volumn 29, Issue 4, 1994, Pages 461-469

  Atsumi, Shigeru ^a   Banba, Hironori ^a   Kuriyama, Masao ^a   Umezawa, Akira ^a   Yamada, Seiji ^a   Ohshima, Yoichi ^a   Oshikiri, Masamitsu ^a   Hiura, Yohei ^a   Yoshikawa, Kuniyoshi ^a   Naruke, Kiyomi ^a   Yamane, Tomoko ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CODING ERRORS; COMPUTER CIRCUITS; DATA STORAGE EQUIPMENT; DECODING; ELECTRIC GENERATORS; GATES (TRANSISTOR); HOT CARRIERS; LOGIC GATES; MAGNETIC DISK STORAGE; MICROPROCESSOR CHIPS; VOLTAGE CONTROL;

FLASH EEPROM; INTERNAL VOLTAGE GENERATOR; MEMORY CELL; NEGATIVE GATE BIASED SCHEME; READ OPERATION FAILURE; ROW DECODER CIRCUIT; SECTOR ERASE OPERATION; SELF CONVERGENCE METHOD; SELF DATA REFRESH OPERATION;

PROM;

EID: 0028419762     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.280696     Document Type: Article

References (17)

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