Optimization of Gate-to-Drain Separation in Submicron Gate-Length Modulation Doped FET’s for Maximum Power Gain Performance

IEEE Transactions on Electron Devices

Volumn 41, Issue 4, 1994, Pages 465-475

  Chen, Jau Wen ^a   Das, Mukunda B ^a   Thurairaj, Mohan ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE CARRIERS; ELECTRIC CURRENT CONTROL; ELECTRIC FIELD EFFECTS; ELECTRIC NETWORK PARAMETERS; ELECTRIC PROPERTIES; ELECTRODES; EQUIVALENT CIRCUITS; GAIN CONTROL; GATES (TRANSISTOR); HETEROJUNCTIONS; SEMICONDUCTING INDIUM COMPOUNDS; SUBSTRATES;

CHARGE CONTROL MODEL; CURRENT EQUATIONS; GATE TO DRAIN SEPARATION OPTIMIZATION; MAXIMUM POWER GAIN PERFORMANCE; OPEN CIRCUIT VOLTAGE GAIN; SUBMICRON GATE LENGTH MODULATION DOPED FIELD EFFECT TRANSISTORS;

FIELD EFFECT TRANSISTORS;

EID: 0028419306     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.278497     Document Type: Article

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