Sub-l-µA Dynamic Reference Voltage Generator for Battery-Operated DRAM’s

IEEE Journal of Solid-State Circuits

Volumn 29, Issue 4, 1994, Pages 448-453

  Tanaka, Hitoshi ^a   Nakagome, Yoshinobu ^a   Etoh, Jun ^a   Aoki, Masakazu ^a   Miyazawa, Kazuyuki ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENT CONTROL; ELECTRIC CURRENTS; ELECTRIC RESISTANCE; INTEGRATED CIRCUIT MANUFACTURE; RANDOM ACCESS STORAGE; RESISTORS; SPURIOUS SIGNAL NOISE; STABILITY; THERMAL EFFECTS;

BATTERY OPERATED DYNAMIC RANDOM ACCESS MEMORIES; CURRENT MIRROR CIRCUITS; REFERENCE VOLTAGE GENERATOR; THRESHOLD VOLTAGE DIFFERENCE GENERATOR; ULTRALOW STANDBY CURRENT; VOLTAGE-UP CONVERTER;

VOLTAGE REGULATORS;

EID: 0028416571     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.280694     Document Type: Article

References (6)

1. K. Sato et al., “A 4Mb pseudo SRAM operating at 2.6V±1V, with 3 µA data retention current,” IEEE J. Solid-State Circuits, vol. 26, pp. 1556-1562, 1991.
2. H. Tanaka et al., “Sub-l-µA dynamical reference voltage generator for battery-operated DRAMs,” in Symp. VLSI Circuits Dig. Tech. Papers, May 1993, pp. 87-88.
3. M. Horiguchi et al., “Dual-regulator dual-decoding-trimmer DRAM voltage limiter for burn-in test,” IEEE J. Solid-State Circuits, vol. 26, pp. 1544-1549, Nov. 1991.
4. K. Ishibashi et al., “A voltage down converter with submicroampere standby current for low-power static RAM’s,” IEEE J. Solid-State Circuits, vol. 27, pp. 920-926, June 1992.
5. P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 2nd ed. New York: Wiley, 1984, ch. 9.
6. P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design. New York: Holt, Rinehart, and Winston, 1987, ch. 11.