A 1.5 V BiCMOS Dynamic Logic Circuit Using a “BiPMOS Pull-Down” Structure for VLSI Implementation of Full Adders

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 41, Issue 4, 1994, Pages 329-332

  Kuo, J B ^a   Chen, S S ^a   Chiang, C S ^a   Su, K W ^a   Lou, J H ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC INVERTERS; ELECTRIC NETWORK ANALYSIS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; LOGIC DESIGN; SEMICONDUCTOR DEVICE STRUCTURES;

BICMOS DYNAMIC LOGIC CIRCUIT; BIPMOS PULLDOWN STRUCTURE; CARRY LOOK AHEAD CIRCUIT; FULL ADDER CIRCUITS;

LOGIC CIRCUITS;

EID: 0028413191     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/81.285691     Document Type: Article

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