4-2 Compressor with complementary pass-transistor logic

IEICE Transactions on Electronics

Volumn E77-C, Issue 4, 1994, Pages 647-649

  Kanie, Youji ^a   Kubota, Yasushi ^a   Toyoyama, Shinji ^a   Iwase, Yasuaki ^a   Tsuchimoto, Shuhei ^a  

^a SHARP CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; FORMAL LOGIC; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; LOGIC GATES; MATHEMATICAL MODELS; MULTIPLEXING EQUIPMENT; TRANSISTORS; TREES (MATHEMATICS);

COMPLEMENTARY PASS TRANSISTOR LOGIC; REGULARLY STRUCTURED WALLACE TREE;

MULTIPLYING CIRCUITS;

EID: 0028405787     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (4)