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Volumn 11, Issue 1, 1994, Pages 7-17

ScanBist: A Multifrequency Scan-Based BIST Method

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL CIRCUITS; DIGITAL DEVICES; EQUIPMENT TESTING; SYNCHRONIZATION;

EID: 0028400628     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.262318     Document Type: Article
Times cited : (22)

References (18)
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    • A. Pancholy, J. Rajski, and L.J. McNaughton, “Empirical Failure Analysis and Validation of Fault Models in CMOS VLSI,” Proc. Int'l Test Conf, IEEE Computer Society Press, Los Alamitos, Calif., 1990, pp. 938–947.
    • (1990) Proc. Int'l Test Conf , pp. 938-947
    • Pancholy, A.1    Rajski, J.2    McNaughton, L.J.3
  • 2
    • 0342694472 scopus 로고
    • Delay Test: The Next Frontier for LSSD Test Systems
    • CS Press
    • Koenemann et al., “Delay Test: The Next Frontier for LSSD Test Systems,” Proc., Int'l Test Conf., CS Press, 1992, pp. 578–587.
    • (1992) Proc., Int'l Test Conf. , pp. 578-587
    • Koenemann1
  • 3
    • 0021521542 scopus 로고
    • LOCST: A Built-In Self-Test Technique
    • Nov.
    • J.J. LeBlanc, “LOCST: A Built-In Self-Test Technique,” IEEE Design & Test of Computers, Vol. 1, No.4, Nov. 1984, pp. 45–52.
    • (1984) IEEE Design & Test of Computers , vol.1 , Issue.4 , pp. 45-52
    • LeBlanc, J.J.1
  • 6
    • 84936902124 scopus 로고    scopus 로고
    • Circuit for Generating Nonoverlapping Two-Phase Clocks
    • U.S. Patent No.4,912,340, Apr.
    • P. Wilcox, S. Sunter, and N. Mehta, “Circuit for Generating Nonoverlapping Two-Phase Clocks,” U.S. Patent No.4,912,340, Apr. 1990.
    • Wilcox, P.1    Sunter, S.2    Mehta, N.3
  • 7
    • 0024125932 scopus 로고
    • Fault Detection Effectiveness of Weighted Random Patterns
    • CS Press
    • J.A. Waicukauski, V.P. Gupta, and S.T. Patel, “Fault Detection Effectiveness of Weighted Random Patterns,” Roc. Int'l Test Conf., CS Press, 1988, pp. 245–255.
    • (1988) Proc. Int'l Test Conf. , pp. 245-255
    • Waicukauski, J.A.1    Gupta, V.P.2    Patel, S.T.3
  • 9
    • 0025480231 scopus 로고
    • A New Procedure for Weighted Random Built-In Self-Test
    • CS Press
    • F. Muradali, V.K. Agarwal, and B. Nadeau-Dostie, “A New Procedure for Weighted Random Built-In Self-Test,” Proc. Int'l Test Conf., CS Press, 1990, pp. 660–669.
    • (1990) Proc. Int'l Test Conf. , pp. 660-669
    • Muradali, F.1    Agarwal, V.K.2    Nadeau-Dostie, B.3
  • 11
    • 0024714960 scopus 로고
    • Cellular Automata-Based Pseudorandom Number Generators for Built-In Self-Test
    • P.D. Hortensius et al., “Cellular Automata-Based Pseudorandom Number Generators for Built-In Self-Test,” IEEE Trans. ICCAD, Vol. 8, 1989, pp. 842–859.
    • (1989) IEEE Trans. ICCAD , vol.8 , pp. 842-859
    • Hortensius, P.D.1
  • 12
    • 0002667079 scopus 로고
    • Skewed-Load Transition Test: Part II, Coverage
    • CS Press
    • S. Patil and J. Savir, “Skewed-Load Transition Test: Part II, Coverage,” Proc. Int'l Test Conf., CS Press, 1992, pp. 714–722.
    • (1992) Proc. Int'l Test Conf. , pp. 714-722
    • Patil, S.1    Savir, J.2
  • 13
    • 84936902125 scopus 로고
    • Application of Scan-Based Design-For-Test Methodology for Static and Timing Failures in VLSI Components
    • B. Dervisoglu and G. Stong, “Application of Scan-Based Design-For-Test Methodology for Static and Timing Failures in VLSl Components,” Proc. Int'l Conf. VLSI, 1991, pp. 10.3.1–10.
    • (1991) Proc. Int'l Conf VLSI , pp. 10.3.1-10
    • Dervisoglu, B.1    Stong, G.2
  • 14
    • 0026388613 scopus 로고
    • Fault Detection and Diagnosis Based On Signature Analysis
    • IEEE, Piscataway, N.J.
    • J. Rajski and J. Tyszer, “Fault Detection and Diagnosis Based On Signature Analysis,” Proc. IEEE Int'l Symp. Circuits and Systems, IEEE, Piscataway, N.J., Vol. 3, 1991, pp.1877-1880.
    • (1991) Proc. IEEE Int'l Symp. Circuits and Systems , vol.3 , pp. 1877-1880
    • Rajski, J.1    Tyszer, J.2
  • 15
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    • Computation of Exact Fault Coverage for Compact Signature Testing Scheme
    • IEEE, Vol.
    • D. Lambidonis et al., “Computation of Exact Fault Coverage for Compact Signature Testing Scheme.” IEEE Int'l Symp. Circuits and Systems, IEEE, Vol. 3, 1991, pp, 1873–1876.
    • (1991) IEEE Int'l Symp. Circuits and Systems , vol.3 , pp. 1873-1876
    • Lambidonis, D.1
  • 16
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    • Scan Design Software for ASICs
    • J. Rajski and J. Tyszer, “Fault Detection and Diagnosis Based On Signature Analysis,” Proc. IEEE Int'l Symp. Circuits and Systems, IEEE, Piscataway, N.J., Vol. 3, 1991, pp. 1877–1880.
    • (1989) Proc. Canadian Conf., on VLSI , pp. 3-8
    • Nadeau-Dostie, B.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.