A Compact Charge Ratio Expression for the Emitter Delay of Polysilicon Emitter Bipolar Transistors

IEEE Transactions on Electron Devices

Volumn 41, Issue 3, 1994, Pages 454-455

  Castaer, Luis M ^a   Sureda, Sonia ^a   Bardés, Daniel ^a   Alcubilla, Ramón ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE CARRIERS; CRYSTALS; GRAIN BOUNDARIES; GRAIN SIZE AND SHAPE; INTERFACES (MATERIALS); MORPHOLOGY; OXIDES; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MODELS;

EMITTER DELAY; POLYSILICON EMITTER BIPOLAR TRANSISTORS;

BIPOLAR TRANSISTORS;

EID: 0028397614     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.275236     Document Type: Article

References (6)

1. M. Namba, T. Kobayashi, T. Uchino, T. Nakamura, M. Kondo, Y. Tamaki, S. Iijima, T. Kure, and M. Tanabe, “A 64 GHz Si bipolar transistor using in-situ phospforus doped polysilicon emitter technology,” IEDM Tech. Dig., pp. 443-446, 1991.
2. Z. Yu, B. Riccó, and R. W. Dutton, “A comprehensive analytical and numerical model of polysilicon emitter contacts in bipolar transistors,” IEEE Trans. Electron Devices, vol. ED-31, pp. 773-784, 1984.
3. L. Castañer and P. Ashburn, “Vertical scalability of forward delay times in bipolar transistors,” IEEE Trans. Electron Devices, vol. 36, pp. 1841-1844, 1989.
4. J. del Alamo, S. E. Swirhun, Y. H. Kwark, and R. M. Swanson, “Simultaneous measurement of hole lifetime, hole mobility and bandgap narrowing in heavily doped n-type silicon,” IEDM Tech. Dig., pp. 290-293, 1985.
5. S. E. Swirhun, Y. H. Kwark, and R. M. Swanson, “Measurement of electron lifetime, electron mobility and bandgap narrowing in heavily doped p-type silicon,” IEDM Tech. Dig., pp. 24-27, 1986.
6. G. R. Wolstenholme, “An investigation of polysilicon emitter transistors,” Ph.D. dissertation, Univ. Southampton, UK, 1988.