A New Patterning Process Concept for Large-Area Transistor Circuit Fabrication Without Using an Optical Mask Aligner

IEEE Transactions on Electron Devices

Volumn 41, Issue 3, 1994, Pages 306-314

  Mikami, Yoshiro ^a   Nagae, Yoshiharu ^a   Mori, Yuji ^a   Kuwabara, Kazuhiro ^a   Saito, Takeshi ^a   Hayama, H ^a   Asada, Hideki ^a   Akimoto, Yasumasa ^a   Kobayashi, Masayoshi ^a   Okazaki, Satoshi ^a   Asaka, Kenji ^a   Matsui, Hiroyuki ^a   Nakamura, Kazunori ^a   Kaneko, Eiji ^a  

^a Giant Electronics Research Laboratory GTC Corporation ^*  (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CONTAMINATION; ETCHING; IMPURITIES; INTEGRATED CIRCUIT MANUFACTURE; LIQUID CRYSTAL DISPLAYS; MASKS; PHOTOLITHOGRAPHY; PHOTORESISTS; SUBSTRATES; THIN FILM CIRCUITS;

DOUBLE LAYER RESIST METHOD; LARGE AREA TRANSISTOR CIRCUIT FABRICATION; LARGE THIN FILM TRANSISTOR LIQUID CRYSTAL DISPLAYS; OPTICAL MASK ALIGNER; PATTERNING PROCESS CONCEPT; THIN FILM TRANSISTORS;

TRANSISTORS;

EID: 0028393269     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.275214     Document Type: Article

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