Hot-Carrier-Reliability Design Guidelines for CMOS Logic Circuits

IEEE Journal of Solid-State Circuits

Volumn 29, Issue 3, 1994, Pages 253-262

  Quader, Khandker N ^a   Minami, Eric R ^a   Wei Jen, W J ^a   Huang, H ^a   Ko, Ping K ^a   Hu, Chenming ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; LOGIC CIRCUITS;

BERT SIMULATIONS; DRAIN CURRENT; HOT CARRIERS;

CMOS INTEGRATED CIRCUITS;

EID: 0028388470     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.278346     Document Type: Article

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