Characteristics of Hebbian-Type Associative Memories with Quantized Interconnections

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 41, Issue 2, 1994, Pages 168-171

  Chung, Pau Choo ^a   Tsai, Ching Tsorng ^a   Sun, Yung Nien ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION THEORY; CHANNEL CAPACITY; COMPUTER HARDWARE; COMPUTER SIMULATION; HEURISTIC METHODS; LINEAR INTEGRATED CIRCUITS; MATHEMATICAL MODELS; NEURAL NETWORKS; OPTIMIZATION; PROBABILITY; THRESHOLD ELEMENTS; VECTORS;

ANALOG CIRCUITS; BINARY MEMORY POINTS; HARDWARE IMPLEMENTATION; HEBBIAN-TYPE ASSOCIATIVE MEMORY; QUANTIZATION; QUANTIZED INTERCONNECTION; STATISTICAL NEURODYNAMICS; STORAGE CAPACITY; TIME DOMAIN BEHAVIOR;

ASSOCIATIVE STORAGE;

EID: 0028377949     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/81.269054     Document Type: Article

References (7)

1. J. J. Hopfield and D. W. Tank, “Neural computation of decisions in optimization problems,” Biol. Cybern., vol. 52, pp. 141–152, 1985.
2. J. H. Wang, T. F. Krile, and J. F. Walkup, “Determination of Hopfield associative memory characteristics using a single parameter,” Neural Networks, vol. 3, pp. 319–331, May 1990.
3. P. C. Chung and T. F. Krile, “Characteristics of Hebbian-type associative memories having faulty interconnections,” IEEE Trans. Neural Networks, vol. 3, pp. 969–980, Nov. 1992.
4. J. H. Wang, T. F. Krile, and J. Walkup, “Reduction of interconnection weights in higher order associative memory networks,” IJCNN, vol. II, pp. 177, July 1991.
5. R. E. Howard, D. B. Schwartz, J. S. Denker, R. W. Epworth, H. P. Graf, W. E. Hubbard, L. D. Jackel, B. L. Straughn, and D. M. Tennant, “An associative memory based on an electronic neural network architecture,” IEEE Trans. Electron Devices, pp. 1553–1556, July 1987.
6. M. Verleysen and B. Sirletti, “A high-storage capacity content-addressable memory and its learning algorithm,” IEEE Trans. Circ. and Syst., pp. 762–766, May 1989.
7. D. E. Van Den Bout and T. H. Miller, “A digital architecture employing stochasticism for the simulation of Hopfield neural nets,” IEEE Trans. Circ. and Syst., pp. 732–738, May 1989.