An Efficient Nonenumerative Method to Estimate the Path Delay Fault Coverage in Combinational Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 13, Issue 2, 1994, Pages 240-250

  Pomeranz, Irith ^a   Reddy, Sudhakar M ^a  

^a UNIVERSITY OF IOWA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION THEORY; CIRCUIT THEORY; COMBINATORIAL CIRCUITS; COMPUTATIONAL COMPLEXITY; ELECTRIC FAULT LOCATION; GATES (TRANSISTOR); LINEAR NETWORK ANALYSIS; PARAMETER ESTIMATION; POLYNOMIALS;

NONENUMERATIVE METHOD; PATH DELAY FAULT COVERAGE; POLYNOMIAL COMPLEXITY;

INTEGRATED CIRCUIT TESTING;

EID: 0028377203     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.259947     Document Type: Article

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