Modeling the I-V Characteristics of Fully Depleted Submicrometer SOI MOSFET's

IEEE Electron Device Letters

Volumn 15, Issue 2, 1994, Pages 45-47

  Hsiao, Tommy C ^a   Kistler, Neal A ^a   Woo, Jason C S ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC PROPERTIES; NUMERICAL ANALYSIS; SEMICONDUCTING FILMS; SILICON ON INSULATOR TECHNOLOGY;

I-V CHARACTERISTICS; SUBMICROMETER DEVICES;

MOSFET DEVICES;

EID: 0028375272     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/55.285378     Document Type: Article

References (13)

1. S. Veeraraghavan and J. G. Fossum, “A physical short-channel model for the thin-film SOI MOSFET applicable to device and circuit CAD,” IEEE Trans. Electron Devices, vol. 35, pp. 1866–1874, 1988.
2. J.-P. Colinge, Silicon-on-Insulator Technology: Material to VLSI, Boston, MA: Kluwer, 1991.
3. C. G. Sodini, P.-K. Ko, and J. L. Moll, “The effect of high fields on MOS device and circuit performance,” IEEE Trans. Electron Devices, vol. 31, pp. 1386–1393, 1984.
4. H.-K. Lim and J. G. Fossum, “Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFET's,” IEEE Trans. Electron Devices, vol. 30, pp. 1244–1251, 1983.
5. K. Mayaram, J. C. Lee, and C. Hu, “A model for the electric field in lightly doped drain structures,” IEEE Trans. Electron Devices, vol. 34, pp. 1509–1518, 1987.
6. T. Y. Chan, P. K. Ko, and C. Hu, “Dependence of channel electric field on device scaling,” IEEE Electron Device Lett., vol. 6, pp. 551–553, 1985.
7. J. Chen, K. Quader, R. Solomon, T. Chan, P. Ko, and C. Hu. “Hot electron gate current and degradation in p-channel SOI MOSFET's,” IEEE 1991 Int. SOI Conf Proc., pp. 8–9, 1991.
8. J. Chen, R. Solomon, T.-Y. Chan, P.-K. Ko, and C. Hu, “A CV technique for measuring thin SOI film thickness,” IEEE Electron Device Lett., vol. 12, pp. 453–455, 1991.
9. P. I. Suciu and R. L. Johnston, “Experimental derivation of the source and drain resistance of MOS transistors,” IEEE Trans. Electron Devices, vol. 27, pp. 1846–1848, 1980.
10. L. T. Su, K. E. Goodson, D. A. Antoniadis, M. I. Filk, and J. E. Chung, “Measurement and modeling of self-heating effects in SOI MOSFET's,” IEDM Tech. Dig., pp. 357–360, 1992.
11. K. K. Young and J. A. Burns, “Avalanche-induced drain-source breakdown in silicon-on-insulator n-MOSFET‘s,” IEEE Trans. Electron Devices, vol. 35, pp. 426–431. 1988.
12. R.J. T. Bunyan, M. J. Uren, J. C. Alderman, and W. Eccleston, “Use of noise thermometry to study the effects of self-heating in submicrometer SOI MOSFET's,” IEEE Electron Device Lett., vol. 13, pp. 279–281, 1992.
13. D. Yachou, J. Gautier, and C. Raynaud, “Self-heating effects on SOI devices and implication to parameter extraction,” IEEE SOI Conf Proc., pp. 148–149, 1993.