-
1
-
-
0003517783
-
Theory and Practice of Error Control Codes
-
MA: Addison-Wesley
-
R. E. Blahut, Theory and Practice of Error Control Codes. Reading, MA: Addison-Wesley, 1983.
-
(1983)
Reading
-
-
Blahut, R.E.1
-
2
-
-
0003516597
-
Error-Control Techniques for Digital Communication
-
New York: Wiley
-
A. M. Michelson and A. H. Levesque, Error-Control Techniques for Digital Communication. New York: Wiley, 1985.
-
(1985)
-
-
Michelson, A.M.1
Levesque, A.H.2
-
3
-
-
0003476270
-
Error Control Coding
-
Englewood Cliffs, NJ: Prentice-Hall
-
S. Lin and D. J. Costellor, Jr., Error Control Coding. Englewood Cliffs, NJ: Prentice-Hall, 1983.
-
(1983)
-
-
Lin, S.1
Costellor, D.J.2
-
4
-
-
0024089121
-
On the VLSI design of a pipeline Reed-Solomon decoder using systolic arrays
-
H. M. Shao and I. S. Reed, “On the VLSI design of a pipeline Reed-Solomon decoder using systolic arrays,” IEEE Trans. Comput., vol. C-37, pp. 1273-1280, 1988.
-
(1988)
IEEE Trans. Comput.
, vol.C-37
, pp. 1273-1280
-
-
Shao, H.M.1
Reed, I.S.2
-
5
-
-
0000539531
-
A construction method of high-speed decoders using ROM's for Bose-Chaudhuri-Hocquenghem and Reed-Solomon codes
-
H. Okano and H. Imai, “A construction method of high-speed decoders using ROM's for Bose-Chaudhuri-Hocquenghem and Reed-Solomon codes,” IEEE Trans. Comput., vol. C-36, pp. 1165-1171, 1987.
-
(1987)
IEEE Trans. Comput.
, pp. 1165-1171
-
-
Okano, H.1
Imai, H.2
-
6
-
-
33749474139
-
A VLSI architecture for implementation of the decoder for binary BCH codes
-
TAiwan, Dec. 9-13
-
C.-L. Wang and W.-J. Bair, “A VLSI architecture for implementation of the decoder for binary BCH codes,” in Proc. Symp. Commun., TAiwan, Dec. 9-13, 1991, pp. 36-40.
-
(1991)
Proc. Symp. Commun.
, pp. 36-40
-
-
Wang, C.-L.1
Bair, W.-J.2
-
7
-
-
84941609329
-
High speed decoder of Reed-Solomon codes
-
to appear
-
S. W. Wei and C. H. Wei, “High speed decoder of Reed-Solomon codes,” IEEE Trans. Commun., to appear.
-
IEEE Trans. Commun.
-
-
Wei, S.W.1
Wei, C.H.2
-
8
-
-
0020207091
-
Bit-serial Reed-Solomon encoders
-
E. R. Beriekamp, “Bit-serial Reed-Solomon encoders,” IEEE Trans. Inform Theory, vol. IT-28, pp. 869-874, 1982.
-
(1982)
IEEE Trans. Inform Theory
, vol.IT-28
, pp. 869-874
-
-
Beriekamp, E.R.1
-
9
-
-
0022108239
-
VLSI architectures for computing multiplications and inverses in GF(2 m ), IEEE Trans. Comput., vol. C-34, pp. 709-716, 1985
-
C. C. Wang et al., “VLSI architectures for computing multiplications and inverses in GF(2 m ), IEEE Trans. Comput., vol. C-34, pp. 709-716, 1985.
-
(1985)
, vol.C-34
, pp. 709-716
-
-
Wang, C.C.1
-
10
-
-
0021411526
-
Systolic multipliers for finite fields GF(2 m ), IEEE Trans. Comput., vol. C-33, pp. 357-360, 1984
-
C.-S. Yeh, S. Reed, and T. K. Truong, “Systolic multipliers for finite fields GF(2 m ), IEEE Trans. Comput., vol. C-33, pp. 357-360, 1984.
-
(1984)
IEEE Trans. Comput
, vol.C-33
, pp. 357-360
-
-
Yeh, C.-S.1
Reed, S.2
Truong, T.K.3
-
11
-
-
0015201038
-
A cellular-array multiplier for GF(2 m ), IEEE Trans. Comput., vol. C-20, pp. 1573-1578, 1971
-
B. A. Laws, Jr. and C. K. Rushforth, “A cellular-array multiplier for GF(2 m ), IEEE Trans. Comput., vol. C-20, pp. 1573-1578, 1971.
-
(1971)
IEEE Trans. Comput
, vol.C-20
, pp. 1573-1578
-
-
Laws, B.A.1
Rushforth, C.K.2
-
12
-
-
0026186630
-
Systolic array implementation of multipliers for finite fields GF(2m)
-
C.-L. Wang and J.-L. Lin, “Systolic array implementation of multipliers for finite fields GF(2m),” IEEE Trans. Circuits Syst., vol. CAS-38, pp. 796800, 1991.
-
(1991)
IEEE Trans. Circuits Syst
, vol.CAS-38
-
-
Wang, C.-L.1
Lin, J.-L.2
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