Zero Waiting-Cycle Hierarchical Block Matching Algorithm and its Array Architectures

IEEE Transactions on Circuits and Systems for Video Technology

Volumn 4, Issue 1, 1994, Pages 18-28

  Wang, Bor Min ^a   Yen, Jui Cheng ^a   Chang, Shyang ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER HARDWARE;

HIERARCHICAL BLOCK MATCHING ALGORITHM; MULTIPROCESSOR ARRAY DATA FLOW ARRANGEMENT; REAL-TIME PROCESSING ARCHITECTURE; ZERO WAITING-CYCLE ALGORITHM (ZWCA);

DATA PROCESSING;

EID: 0028372042     PISSN: 10518215     EISSN: 15582205     Source Type: Journal    
DOI: 10.1109/76.276169     Document Type: Article

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