Multiprocessor architecture for multiple path stack sequential decoders

IEEE Transactions on Communications

Volumn 42, Issue 2 -4 pt 2, 1994, Pages 951-957

  Belanger, Normand ^a   Haccoun, David ^a   Savaria, Yvon ^a  

^a ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; DATA COMMUNICATION SYSTEMS; ERROR CORRECTION; SIGNAL PROCESSING;

CONVOLUTIONAL CODES; MULTIPLE PATH; STACK SEQUENTIAL DECODER; VITERBI ALGORITHM;

DECODING;

EID: 0028371717     PISSN: 00906778     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (12)