Measurement of MOS Current Mismatch in the Weak Inversion Region

IEEE Journal of Solid-State Circuits

Volumn 29, Issue 2, 1994, Pages 138-142

  Forti, Francesco ^a   Wright, Michael E ^b  

^a INFN SEZIONE DI PISA   (Italy)

^b LAWRENCE BERKELEY NATIONAL LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENT MEASUREMENT; INTEGRATED CIRCUITS; SOLID STATE DEVICES;

CURRENT MISMATCH; MOS TRANSISTORS; THRESHOLD MATCHING;

MOS DEVICES;

EID: 0028369135     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.272119     Document Type: Article

References (6)

1. J.-B. Shyu, G. Temes, and K. Yao, “Random errors in MOS capacitors,” IEEE J. Solid-State Circuits, vol. SC-17, pp. 1070-1076, Dec. 1982.
2. J.-B. Shyu, G. C. Temes, and F. Krummenacher, “Random effects in matched MOS capacitors and current sources,” IEEE J. Solid-State Circuits, vol. SC-19, pp. 948-955, Dec. 1984.
3. M. J. Pelgrom, A. C. Duinmaijer, and A. P. Welbers, “Matching properties of MOS transistors,” IEEE J. Solid-State Circuits, vol. 24, pp. 1433-1440, Oct. 1989.
4. T.-W. Pan and A. Abidi, “A 50-dB variable gain amplifier using parasitic bipolar transistors in CMOS,” IEEE J. Solid-State Circuits, vol. 24, pp. 951-961, Aug. 1989.
5. R. Buckingham, Numerical Methods. London: Pitman and Sons, 1962.
6. K. R. Lakshmikumar, R. Hadaway, and M. Copeland, “Characterization and modeling of mismatch in MOS transistors for precision analog design,” IEEE J. Solid-State Circuits, vol. SC-21, pp. 1057-1066, Dec. 1986.