A Bipolar Four-Quadrant Analog Quarter-Square Multiplier Consisting of Unbalanced Emitter-Coupled Pairs and Expansions of its Input Ranges

IEEE Journal of Solid-State Circuits

Volumn 29, Issue 1, 1994, Pages 46-55

  Kimura, Katsuji ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; CIRCUIT THEORY; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; EMITTER COUPLED LOGIC CIRCUITS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; LINEAR INTEGRATED CIRCUITS; MATHEMATICAL MODELS; POWER SUPPLY CIRCUITS;

BIPOLAR FOUR QUADRANT ANALOG QUARTER SQUARE MULTIPLIER; GILBERT MULTIPLIER; SQUARING UNIT; UNBALANCED EMITTER COUPLED PAIRS;

MULTIPLYING CIRCUITS;

EID: 0028338159     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.272093     Document Type: Article

References (6)

1. B. Gilbert, “A precise four-quadrant multiplier with subnanosecond response,” IEEE J. Solid-State Circuits, vol. SC-3, no. 4, pp. 365-373, Dec. 1968.
2. B. Gilbert, “A high-performance monolithic multiplier using active feedback,” IEEE J. Solid-State Circuits, vol. SC-9, no. 6, pp. 364-373, Dec. 1974.
3. K. Kimura, “A unified analysis of four-quadrant analog multipliers operable on low supply voltage,” IEICE Trans. Electron., vol. E-76-C, no. 5, pp. 714-737, May 1993.
4. K. Kimura, “Some circuit design techniques for bipolar and MOS pseudologarithmic rectifiers operable on low supply voltage,” IEEE Trans. Circuits Syst.—I, vol. 39, no. 9, pp. 78-83, Sept. 1992.
5. H. Tanimoto, M. Koyama, and Y. Yoshida, “Realization of a 1-V active filter using a linearization technique employing plurality of emitter-coupled coupled pairs,” IEEE J. Solid-State Circuits, vol. 26, no. 7, July 1991.
6. NEC User's Manual, CHS Family Analog Master Version 1.0, pp. 57-60, July 1992.