CMOS-SRAM soft-error simulation system

Annual Proceedings - Reliability Physics (Symposium)

Volumn , Issue , 1994, Pages 339-343

  Satoh, Shigeo ^a   Sudo, Ritsuo ^a   Tashiro, Hiroko ^a   Higaki, Naoshi ^a   Nakayama, Noriaki ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALPHA PARTICLES; CHARGE CARRIERS; ELECTRIC CURRENTS; EQUIVALENT CIRCUITS; ERRORS; INTEGRATED CIRCUIT LAYOUT; MASKS; MATHEMATICAL MODELS; RANDOM ACCESS STORAGE; SEMICONDUCTOR STORAGE;

ALPHA PARTICLE EMISSION RATES; CMOS SRAM CELLS; MASK LAYOUT; NOISE CURRENT MODEL; PROCESS CONDITIONS; SOFT ERROR RATES;

CMOS INTEGRATED CIRCUITS;

EID: 0028271293     PISSN: 00999512     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/relphy.1994.307815     Document Type: Conference Paper

References (9)