Large Dynamic Range Computations over Small Finite Rings

IEEE Transactions on Computers

Volumn 43, Issue 1, 1994, Pages 78-86

  Wigley, Neil M ^a   Jullien, Graham A ^a   Reaume, Daniel ^a  

^a UNIVERSITY OF WINDSOR   (Canada)

Author keywords

Complex arithmetic; dynamic logic; inner prod ; polynomial rings; quadratic residue rings; residue number systems; uct computations; VLSI signal processors

Indexed keywords

ALGORITHMS; FAST FOURIER TRANSFORMS; SIGNAL PROCESSING;

COMPLETE QUANTIZATION ANALYSIS; FAST FOURIER TRANSFORM ALGORITHM; MODULUS REPLICATION RESIDUE NUMBER SYSTEM (NRRNS); MULTIVARIABLE MAPPING STRATEGY; SCALING STRATEGY; VERY LARGE SCALE INTEGRATION IMPLEMENTATION STRATEGIES;

VLSI CIRCUITS;

EID: 0028262751     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.250611     Document Type: Article

References (14)

1. R. E. Blahut, Fast Algorithms for Digital Signal Processing. Reading, MA: Addison-Wesley, 1985.
2. M. K. Chu and D. I. Pulfrey, “Design procedures for differential cascode-voltage switch circuits,” IEEE Trans. Solid-State Circuits, vol. SC-21, pp. 1082-1087, 1986.
3. R. Godement, Algebra. Paris: Hermann (English translation Boston: Houghton Mifflin), 1968.
4. G. A. Jullien, “Bit-level systolic arrays for high speed DSP,” Advances in VLSI Signal Processing. Norwood, NJ: Ablex, 1991.
5. G. A. Jullien, P. D. Bird, J. T. Carr, M. Taheri, and W. C. Miller, “An efficient bit-level systolic cell design for finite ring digital signal processing applications,” J. VLSI Sig. Proc., vol. I, pp. 189-208, 1989.
6. G. A. Jullien, M. Taheri, S. Bandyopadhyay, and W. C. Miller, “A low-overhead scheme for testing a bit level finite ring systolic array,” J. VLSI Sig. Proc., vol. I, no. 4, 1989.
7. L. R. Rabiner and B. Gold, Theory and Application of Digital Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, 1975.
8. M. A. Soderstrand, W. K. Jenkins, G. A. Jullien, and F. J. Taylor, Residue Number System Arithmetic: Modern Applications in Digital Signal Processing. 1986.
9. M. Taheri, G. A. Jullien, and W. C. Miller, “High-speed signal processing using systolic arrays over finite rings,” IEEE Trans. Selected Areas Commun., vol. 6, pp. 504-512, 1988.
10. B-D, Tseng, G. A. Jullien, and W. C. Miller, “Implementation of FFT structures using the residue number system,” IEEE Trans. Comput., vol. 28, pp. 831-844, 1979.
11. N. M. Wigley and G. A. Jullien, “On moduli replication for residue arithmetic computations of complex inner products,” IEEE Trans. Comput., vol. 39, pp. 1065-1076, 1990.
12. J. Yuan and C. Svennson, “High-speed CMOS circuit technique,” IEEE/J. Solid-State Circuits, vol. 24, pp. 62-70, 1989.
13. D. Zhang, G. A. Jullien, W. C. Miller, and E. Swartzlander, “Arithmetic for digital neural networks,” in Proc. 10th Int. Symp. Computer Arithmetic, 1991, pp. 58-63.
14. G. A. Jullien, W. C. Miller, R. Grondin, Z. Wang, D. Zhang, L. Del Pup, and S. Bizzan, “WoodChuck: A low-level synthesizer for dynamic pipelined DSP arithmetic logic blocks,” in Proc. IEEE Int. Symp. Circuits and Syst., vol. 1, 1992, pp. 176-179.