Dynamic Computational Blocks for Bit-Level Systolic Arrays

IEEE Journal of Solid-State Circuits

Volumn 29, Issue 1, 1994, Pages 14-22

  Jullien, Graham A ^a   Miller, William C ^a   Grondin, Roger ^a   Bizzan, Sami S ^a   Pup, Lino Del ^b   Zhang, Dapeng ^a  

^a UNIVERSITY OF WINDSOR   (Canada)

^b NORTEL NETWORKS   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CRITICAL PATH ANALYSIS; DIGITAL SIGNAL PROCESSING; ELECTRIC NETWORK ANALYSIS; FLIP FLOP CIRCUITS; FORMAL LOGIC; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; MICROPROCESSOR CHIPS; MINIMIZATION OF SWITCHING NETS; SWITCHING CIRCUITS; TREES (MATHEMATICS);

BIT LEVEL SYSTOLIC ARRAYS; DYNAMIC COMPUTATIONAL BLOCKS; INTEGRATED DYNAMIC LOGIC TREES; PIPELINED SWITCHING TREES;

CELLULAR ARRAYS;

EID: 0028262002     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.272090     Document Type: Article

References (12)

1. M. Afghahi and C. Svensson, “A unified single-phase clocking scheme for VLSI systems,” IEEE J. Solid-State Circuits, vol. 25, pp. 225-233, Feb. 1990.
2. J. Yuan and C. Svennson, “High-speed CMOS circuit technique,” IEEE J. Solid-State Circuits, vol. 24, pp. 62-70, 1989.
3. A. J. McAuley, “Dynamic asynchronous logic for high-speed CMOS systems,” IEEE J. Solid-State Circuits, vol. 27, pp. 382-388, 1992.
4. J. V. McCanny and J. G. McWhirter, “Optimized bit level systolic array for convolution,” Proc. Inst. Elec. Eng., part G, vol. 131, no. 6, pp. 632-637, Oct. 1984.
5. M. Taheri, G. A. Jullien, and W. C. Miller, “High speed signal processing using systolic arrays over finite rings,” IEEE Trans. Select. Areas Commun., vol. 6, no. 3, 1988.
6. P. J. Song and G. DeMichell, “Circuits and architecture trade-offs for high speed multiplication,” IEEE J. Solid-State Circuits, vol. 26, no. 9, pp. 1184-1198, 1991.
7. M. K. Chu and D. I. Pulfrey, “Design procedures for differential cascode-voltage switch circuits,” IEEE Trans. Solid-State Circuits, vol. SC-21, no. 6, pp. 1082-1087, 1986.
8. R. E. Bryant, “Graph-based algorithms for boolean function manipulation,” IEEE Trans. Comput., vol. C-35, no. 8, pp. 677-691, 1986.
9. G. A. Jullien, W. C. Miller, R. Grondin, Z. Wang, D. Zhang, L. Del Pup, and S. Bizzan, “WoodChuck: A low-level synthesizer for dynamic pipelined DSP arithmetic logic blocks,” in Proc. IEEE Int. Symp. Circuits and Systems, vol. 1, 1992, pp. 176-179.
10. M. Shoji, “FET scaling in domino CMOS gates,” IEEE J. Solid-State Circuits, vol. SC-20, pp. 1067-1071, 1985.
11. W. C. Elmore, “The transit response of damped linear networks with particular regard to wideband amplifiers,” J. Appl. Phys., vol. 19, no. 1, pp. 55-63, Jan. 1948.
12. S. Bizzan, G. A. Jullien, and W. C. Miller, “Analytical approach to sizing NFET chains,” IEE Electron. Lett., vol. 28, no. 14, pp. 1334-1335, July 1992.