Designing latchup robustness in a 0.35 μm technology

Annual Proceedings - Reliability Physics (Symposium)

Volumn , Issue , 1994, Pages 280-285

  Amerasekera, Ajith ^a   Selvam, S Tamizh ^a   Chapman, Richard A ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; PARAMETER ESTIMATION; ROBUSTNESS (CONTROL SYSTEMS); SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE STRUCTURES; SENSITIVITY ANALYSIS;

DEEP SUBMICRON TECHNOLOGY; HOLDING VOLTAGES; LATCHUP ROBUSTNESS; TRIGGER CURRENTS;

CMOS INTEGRATED CIRCUITS;

EID: 0028257885     PISSN: 00999512     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)