An Integrated CMOS Mixed-Mode Signal Processor for Disk Drive Read Channel Applications

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 41, Issue 1, 1994, Pages 1-11

  Chowdhury, Rahim F ^e  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b Media Vision Inc   (United States)

^c Pericom Semiconductor   (United States)

^d Cirrus Logic   (United States)

^e MAXIM INTEGRATED PRODUCTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; CONSTRAINT THEORY; INTEGRATED CIRCUIT LAYOUT; MAGNETIC DISK STORAGE; PHASE LOCKED LOOPS; PIPELINE PROCESSING SYSTEMS; SIGNAL DETECTION; SIGNAL ENCODING; SIGNAL FILTERING AND PREDICTION;

DATA RATES; MIXED MODE SIGNAL PROCESSOR; PROGRAMMABILITY; READ CHANNEL; ZONED BIT RECORDING;

SIGNAL PROCESSING;

EID: 0028201199     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.275667     Document Type: Article

References (15)

1. Beomsup Kim, David N. Helman and Paul R. Gray, “A 30 MHz High-Speed Analog/Digital PLL in 2 Micron CMOS,” in ISSCC Dig. Tech. Papers, pp. 104–105, Feb. 1990.
2. T. Schmerbeck, R. Richetta and L. Smith, “A 27-MHz Mixed Analog/Digital Magnetic Recording Channel DSP Using Partial Response Signaling with Maximum-Likelyhood Detection,” in ISSCC Dig. Tech. Papers, pp. 136–137, Feb. 1991.
3. B. Kim, J. Greco, D. Helman, H. Yang, S. Wu and R. Chowdhury, “A High-Speed Digital Data Separator Design using Real Time DSP for Disk Drive Applications,” in Proc. IEEE Int. Symp. Circuits Syst., pp. 625–628, June 1992.
4. Janos Kovacs and Wyn Palmer, “A 32-Mb/s Fully-Integrated Read Channel for Disk-Drive Applications”, in ISSCC Dig. Tech. Papers, pp. 62–63 Feb. 1992.
5. G. A. De Veirman and R. G. Yamasaki, “A 27 MHz Programmable Bipolar 0.05° Equiripple Linear-Phase Lowpass Filter,” in ISSCC Dig. Tech. Papers, pp. 64–65 Feb. 1992.
6. US Patent 4,584,695, National Semiconductor, 1980.
7. W. Llewellyn, M. Wong, G. Tietz and P. Tucci, “A 33 Mb/s Data Recovery Phase-Locked Loop,” in ISSCC Dig. Tech. Papers, pp. 12–13 Feb. 1988.
8. H. M. Sierra, An Introduction to Direct Access Storage Devices, San Diego: Academic Press Inc., 1990.
9. V. Gopinathan and Y. Tsividis, “A 5V 7th Order Elliptic Analog Filter for Digital Video Applications,” in ISSCC Dig. Tech. Papers, pp. 208–209, Feb. 1990.
10. J. M. Khoury, “Design of a 15-MHz CMOS Continuous-Time Filter with On-Chip Tuning,” IEEE J. Solid-State Circuits, Vol. 26, No. 12, Dec. 1991, pp. 1988–1997.
11. W. Wu, H. Yang, J. Greco, B. Kim and R. Chowdhury, “All CMOS Analog Pulse Detection System for Data Storage Applications,” in Proc. IEEE Int. Symp. Circuits Syst., pp. 2017–2020, June 1992.
12. F. M. Gardner, Phaselock Techniques, New York: Wiley-Interscience Publication, 1979.
13. M. L. Honig and D. G. Messerschmitt, Adaptive Filters: Structures, Algorithms, and Applications, Boston: Kluwer Academic Publishers, 1984.
14. B. Kim, “Optimal MMSE Gear-Shifting Algorithm for the Fast Synchronization of DPLL,” in Proc. Int. Symp. on Circuits and Syst., pp. 172–175, May 1993.
15. B. Kim, “High Speed Clock Recovery in VLSI Using Hybrid Analog/Digital Techniques,” Memorandum No. UCB/ERL M90/50, June 6th, 1990.