Automatic synthesis and the cost of testing

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1994, Pages 132-135

  Marchok, Thomas E ^a   Maly, Wojciech ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; COSTS; ELECTRIC NETWORK SYNTHESIS; FINITE AUTOMATA; FLIP FLOP CIRCUITS; LOGIC GATES; OPTIMIZATION; PERFORMANCE; REDUNDANCY; SEQUENTIAL CIRCUITS;

AUTOMATIC SYNTHESIS; COMBINATIONALLY REDUNDANT FAULTS; COST OF TESTING; FAULT FREE CIRCUIT; FINITE STATE MACHINE; RETIMING; SEQUENTIALLY REDUNDANT FAULTS; STATE TRANSITION GRAPH; SYNTHESIS TOOLS; TESTABILITY;

INTEGRATED CIRCUIT TESTING;

EID: 0028134488     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)