Video DSP with a macroblock-level-pipeline and a SIMD type vector-pipeline architecture for MPEG2 CODEC

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 1994, Pages 14-15

  Toyokura, M ^a   Saishi, M ^a   Kurohmaru, S ^a   Yamauchi, K ^a   Imanishi, H ^a   Ougi, T ^a   Watabe, A ^a   Matsumoto, Y ^a   Morishige, T ^a   Kodama, H ^a   Miyagoshi, E ^a   Okamoto, K ^a   Gjon, M ^a   Minemaru, T ^a   Ohtani, A ^a   Araki, T ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL DEVICES; ELECTRONIC EQUIPMENT; MICROPROCESSOR CHIPS; PIPELINE PROCESSING SYSTEMS; SCHEMATIC DIAGRAMS; VIDEO SIGNAL PROCESSING;

COMMUNICATION INTERFACE BETWEEN CHIPS; MOTION ESTIMATION; SINGLE INSTRUCTION MULTIPLE DATA STREAM; SOURCE DATA INPUT INTERFACE; VECTOR PIPELINE;

DIGITAL SIGNAL PROCESSING;

EID: 0028126174     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)