Timing analysis of combinational circuits using ADD's

Proceedings of the European Design and Test Conference

Volumn , Issue , 1994, Pages 625-629

  Bahar, R Iris ^a   Cho, Hyunwoo ^a   Hachtel, Gary D ^a   Macii, Enrico ^a   Somenzi, Fabio ^a  

^a UNIVERSITY OF COLORADO   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN ALGEBRA; CRITICAL PATH ANALYSIS; DATA STRUCTURES; DECISION TABLES; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; ELECTRIC NETWORK TOPOLOGY; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; VECTORS;

ALGEBRAIC DECISION DIAGRAMS; CRITICAL CIRCUIT PATHS; CRITICAL GATES; CRITICAL INPUT VECTORS; SYMBOLIC ALGORITHMS; TIMING ANALYSIS;

COMBINATORIAL CIRCUITS;

EID: 0028124073     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (20)