Characterization and reduction of simultaneous switching noise for a multilayer package

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 1994, Pages 949-956

  Hirano, Naohiko ^a   Miura, Masayuki ^a   Hiruta, Yoichi ^a   Sudo, Toshio ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENT MEASUREMENT; ELECTRIC CURRENTS; ELECTRIC PROPERTIES; ELECTROMAGNETIC FIELDS; ESTIMATION; INDUCTANCE MEASUREMENT; MATHEMATICAL MODELS; SEMICONDUCTOR DEVICES; SIGNAL NOISE MEASUREMENT; SIMULATION; SPURIOUS SIGNAL NOISE;

ELECTRIC CURRENT PATH; ELECTROMAGNETIC FIELD SIMULATION; GROUND PIN; MULTILAYER PACKAGE; SIMULTANEOUS SWITCHING NOISE; TEST CHIP;

ELECTRONICS PACKAGING;

EID: 0028074156     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)