Feasibility of using compression to increase memory system performance

Proceedings of the IEEE International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems

Volumn , Issue , 1994, Pages 107-113

  Wang, Jenlong ^a   Quong, Russell W ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SIMULATION; COMPUTER SYSTEMS; DATA STORAGE EQUIPMENT; HIERARCHICAL SYSTEMS; PERFORMANCE; PROGRAM COMPILERS; PROGRAM PROCESSORS;

ACCESS LATENCY; CACHE; DECOMPRESSION DELAY; MEMORY ACCESS TIME; MEMORY SIZE; MISS PENALTIES; MISS RATES; MULTILEVEL MEMORY SYSTEM;

DATA COMPRESSION;

EID: 0028058399     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)