Predicting circuit performance using circuit-level statistical timing analysis

Proceedings of the European Design and Test Conference

Volumn , Issue , 1994, Pages 332-337

  Brashear, Ronn B ^a   Menezes, Noel ^a   Oh, Chanhee ^a   Pillage, Lawrence T ^a   Mercer, M Ray ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CRITICAL PATH ANALYSIS; ELECTRIC NETWORK ANALYSIS; LOGIC CIRCUITS; LOGIC GATES; MATHEMATICAL MODELS; MONTE CARLO METHODS; PERFORMANCE; PROBABILITY; SENSITIVITY ANALYSIS; STATISTICAL TESTS;

CIRCUIT LEVEL STATISTICAL TIMING ANALYSIS; DELAY MODELING; MINIMUM PROPAGATABLE PULSE WIDTH; RESPONSE SURFACE METHODS; SOFTWARE PACKAGE SPICE; TRIPLE NODE DELAY MODEL;

INTEGRATED CIRCUITS;

EID: 0027987599     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)