3.84GIPS integrated memory array processor LSI with 64 processing elements and 3Mb SRAM

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 1994, Pages 260-261

  Yamashita, Nobuyuki ^a   Kimura, Tohru ^a   Fujita, Yoshihiro ^a   Aimoto, Yoshiharu ^a   Manabe, Takashi ^a   Okazaki, Shin'ichiro ^a   Nakamura, Kazuyuki ^a   Yamashina, Masakazu ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAYS; FABRICATION; IMAGE PROCESSING; MICROPROCESSOR CHIPS; SCHEMATIC DIAGRAMS;

BLOCK REPLACEMENT REDUNDANCY; HIGH BANDWIDTH SYSTEMS; INTEGRATED MEMORY ARRAY PROCESSOR; SINGLE INSTRUCTION MULTIPLE DATA STREAM; SRAM; STATIC MEMORY;

RANDOM ACCESS STORAGE;

EID: 0027985861     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)