Interconnect design using convex optimization

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1994, Pages 549-552

  Sancheti, Piyush K ^a   Sapatnekar, Sachin S ^a  

^a IOWA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CONSTRAINT THEORY; DELAY CIRCUITS; ELECTRIC NETWORK ANALYSIS; EQUIVALENT CIRCUITS; HEURISTIC PROGRAMMING; INTEGRATED CIRCUIT LAYOUT; LARGE SCALE SYSTEMS; OPTIMIZATION; TREES (MATHEMATICS);

CONVEX PROGRAMMING FORMULATION; CRUDE DELAY MODEL; ELMORE DELAY MODEL; INTERCONNECT DELAY; TIMING OPTIMIZATION;

ELECTRIC WIRING;

EID: 0027940784     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)