SOI for a 1-Volt CMOS Technology and Application to a 512kb SRAM with 3.5 ns Access Time

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1993, Pages 813-816

  Shahidi, G G ^a   Ning, T H ^a   Chappell, T I ^a   Comfort, J H ^a   Chappell, B A ^a   Franch, R ^a   Anderson, C J ^a   Cook, P W ^a   Schuster, S E ^a   Rosenfield, M G ^a   Polcari, M R ^a   Dennard, R H ^a   Davari, B ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CAPACITANCE; POWER SUPPLY CIRCUITS; RANDOM ACCESS STORAGE; SUBSTRATES;

% REDUCTIONS; ACCESS TIME; BODY EFFECT; CMOS TECHNOLOGY; DRAIN BIAS; FLOATING BODY EFFECT; JUNCTION CAPACITANCES; LOW VOLTAGES; SUBTHRESHOLD SLOPE; TECHNOLOGIES AND APPLICATIONS;

CAPACITANCE; CMOS INTEGRATED CIRCUITS;

ACCESS TIME; FLOATING BODY EFFECTS; SILICON ON INSULATOR (SOI);

EID: 0027889411     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. A. Sekiyama et al, "A 1 V Operating 256-Kbit Full CMOS", Dig. of Symp. VLSI Circuits, p 53(1990).
2. G. Shahidi et al, "A 300K 0.1 µm CMOS on SOI", Tech. Dig. of Symp. on VLSI Tech., p 53(1993).
3. T. I. Chappell et al, "A 2ns Cycle, 3.8 nS Access 512Kb CMOS ECL with a Fully Pipelined Architecture", IEEE Jour, of Soild State Circuits, p 1577(1991).