Reliability of CVD Cu Buried Interconnections

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1993, Pages 265-268

  Cho, James S H ^a   Kang, Ho Kyu ^a   Ryu, Changsup ^a   Wong, S Simon ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALUMINUM ALLOYS; BINARY ALLOYS; COPPER; DIFFUSION BARRIERS; INTEGRATED CIRCUIT INTERCONNECTS; TITANIUM ALLOYS; DIELECTRIC MATERIALS; ELECTRIC CONNECTORS; SEMICONDUCTOR DEVICE MANUFACTURE; ULSI CIRCUITS;

AL-ALLOY; CONFORMALITY; CU DIFFUSION; CU INTERCONNECTIONS; HIGH ASPECT RATIO; LARGE AREA DIODES;

ASPECT RATIO; CHEMICAL VAPOR DEPOSITION;

ASPECT RATIO; BURIED INTERCONNECTION; DIFFUSION BARRIERS; PRECURSOR;

EID: 0027889402     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. E.K. Broadbent, J.M. Flanner, W.G.M Van Der Hoek, I-W.H. Con-nick, "High-Density High-Reliability Tungsten Interconnection by Filled Interconnect Groove Metallization," IEEE Trans. Elec. Dev., pp. 952-956, 1988.
2. A.K. Krishnan, C. Xie, N. Kumar, J. Curry, D. Duane, S. P. Murarka, "Copper Metallization for VLSI Application," Proc. VMIC, pp. 226-231, 1992.
3. M.J. Hampden-Smith and T.T. Kodas, "Copper Etching: New Chemical Approaches," MRS Bulletin, pp. 39-45, 1993.
4. J.P. McVittie, J.C. Rey, L.Y. Cheng, M.M. IslamRaja and K.C. Saraswat, "LPCVD Profile Simulation Using a Re-emission Model," IEEE IEDM Digest, pp. 917-920, 1990.
5. J.S.H. Cho, H-K. Kang, I. Asano, and S.S. Wong, "CVD Cu Interconnections for ULSI," IEEE IEDM Digest, pp. 297-300, 1992.
6. H-K. Kang, I. Asano, C. Ryu, and S.S. Wong, "Grain Structure and Electromigration Properties of CVD Cu Metallization," Proc. VMIC, pp 223-229, 1993.