A 10-b 100-Msample/s Pipelined Subranging BiCMOS ADC

IEEE Journal of Solid-State Circuits

Volumn 28, Issue 12, 1993, Pages 1180-1186

  Sone, Kazuya ^a   Nishida, Yoshio ^a   Nakadai, Naotoshi ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; VIDEO SIGNAL PROCESSING;

BIPOLAR PROCESSES; SUBRANGING ARCHITECTURES; TIMING DIAGRAM;

IMAGE PROCESSING;

EID: 0027888086     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.261990     Document Type: Article

References (11)

1. Y. Ninomiya, “VLSIs for HDTV systems,” in VLSI Circuits Symp. Dig. Tech. Papers, May 1991, pp. 1–4.
2. R. Petschacher et al., “A 10-b 75-MSPS subranging A/D converter with integrated sample and hold,” IEEE J. Solid-State Circuits, vol. SC-25, pp. 1339–1346, Dec. 1990.
3. W. T. Colleran T. H. Phan, and A. A. Abidi, “A 10b, 100 Ms/s pipelined A/D converter,” in ISSCC Dig. Tech. Papers, Feb. 1993, pp. 68–69.
4. C. Lane, “A 10-bit 60 MSPS flash ADC,” in Proc. Bipolar Circuits Tech. Meet., Sept. 1989, pp. 44–47.
5. H. Kimura et al,. “A 10b 300 MHz interpolated-parallel A/D converter,” in VLSI Circuits Symp. Dig. Tech. Papers, June 1992, pp. 94–95.
6. M. Yotsuyanagi et al., “A 12bit 5 µsec CMOS recursive ADC with 25 mW power consumption,” in Proc. CICC, May 1989, pp. 6.4.1-4.
7. K. Sone et al., “An 8-bit 20 MHz subranging ADC with internal clamp and S/H circuits,” in ICCE Dig. Tech. Papers, June 1990, pp. 248–249.
8. M. J. Chambers and L. F. Linder, “A precision monolithic sample-and-hold for video analog-to-digital converters,” in ISSCC Dig. Tech. Papers, Feb. 1991, pp. 168–169.
9. J. Doernberg, P. R. Gray, and D. A. Hodges, “A 10-bit 5-Msample/s CMOS two-step flash ADC,” IEEE J. Solid-State Circuits, vol. SC-24, pp. 241–249, Apr. 1989.
10. H. J. M. Veendrick, “The behavior of flip-flops used as synchronizers and prediction of their failure rate,” IEEE J. Solid-State Circuits, vol. SC-15, pp. 160–176, Apr. 1980.
11. “Dynamic performance testing of A to D converters,” Hewlett Packard Product Note 5180A-2.