A 10-b 20-MHz 30-mW Pipelined Interpolating CMOS ADC

IEEE Journal of Solid-State Circuits

Volumn 28, Issue 12, 1993, Pages 1200-1206

  Kusumoto, Keiichi ^a   Matsuzawa, Akira ^a   Murata, Kenji ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; VIDEO CAMERAS; VIDEO SIGNAL PROCESSING;

ADC ARCHITECTURE; CAPACITATIVE INTERPOLATION; CHOPPER INVERTERS;

CMOS INTEGRATED CIRCUITS;

EID: 0027887674     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.261992     Document Type: Article

References (5)

1. B.-S. Song et al., “A 10 b 15 MHz recycling two-step A/D converter,” in 1SSCC Dig. Tech. Papers, Feb. 1990, pp. 158–159.
2. A. Matsuzawa et al., “A 10 b 30 MHz two-step parallel BiCMOS ADC with internal S/H,” in 1SSCC Dig. Tech. Papers, Feb. 1990, pp. 162–163.
3. T. Matsuura et al., “A 95 mW, 10-b 15 MHz low-power CMOS ADC using analog double-sampled pipelining scheme,” in Symp. VLSI Circuit Dig. Tech. Papers, June 1992, pp. 98–99.
4. N. Fukushima et al., “A CMOS 40 MHz 8 b 105 mW two-step ADC,” in ISSCC Dig. Tech. Papers, Feb. 1989, pp. 14–15.
5. K. Kattmann et al., “A technique for reducing differential nonlinearity errors in flash A/D converters,” in ISSCC Dig. Tech. Papers, Feb. 1991, pp. 170–171.