Statistical timing optimization of combinational logic circuits

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1993, Pages 77-80

  Jyu, Horng Fei ^a   Malik, Sharad ^a  

^a PRINCETON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; LOGIC GATES; MATHEMATICAL MODELS; OPTIMIZATION; PERFORMANCE; PROBABILITY; VLSI CIRCUITS;

PROBABILITY DISTRIBUTIONS; STATISTICAL DELAY; STATISTICAL TIMING BEHAVIOR;

COMBINATORIAL CIRCUITS;

EID: 0027886460     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)