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Volumn 16, Issue 8, 1993, Pages 893-901

An 820 Pin PGA for Ultralarge-Scale BiCMOS Devices

Author keywords

[No Author keywords available]

Indexed keywords

BONDING; ELECTRIC PROPERTIES; ELECTRONICS PACKAGING; FATIGUE TESTING; RELIABILITY; THERMAL EFFECTS;

EID: 0027886135     PISSN: 01486411     EISSN: None     Source Type: Journal    
DOI: 10.1109/33.273690     Document Type: Article
Times cited : (9)

References (8)
  • 1
    • 84939365161 scopus 로고
    • 0.5 µm BiCMOS ASIC family
    • presented at the 1990: CICC, New Products, Session 2
    • T. Mori, T. Yoshimori, H. Muraoka, J. Ohno, T. Sakurai, and T. Sakaue, “0.5 µm BiCMOS ASIC family,” presented at the 1990: CICC, New Products, Session 2, 1992.
    • (1992)
    • Mori, T.1    Yoshimori, T.2    Muraoka, H.3    Ohno, J.4    Sakurai, T.5    Sakaue, T.6
  • 2
    • 0020943244 scopus 로고
    • A 1.0 µm n-well CMOS/bipolar technology for VLSI circuits
    • Dec.
    • J. Miyamoto, “A 1.0 µm n-well CMOS/bipolar technology for VLSI circuits,” in Proc. IEEE IEDM 1983, Dec. 1983, pp. 63–66.
    • (1983) Proc. IEEE IEDM 1983 , pp. 63-66
    • Miyamoto, J.1
  • 5
    • 10844240777 scopus 로고
    • Optimized ground pin assignment in a multilayer package to minimize the simultaneous switching noise
    • Yokohama, Japan, June
    • Y. Hiruta, N. Hirano, and T. Sudo, “Optimized ground pin assignment in a multilayer package to minimize the simultaneous switching noise,” Proc. IMC 1992, Yokohama, Japan, June 1992, pp. 435–440.
    • (1992) Proc. IMC 1992 , pp. 435-440
    • Hiruta, Y.1    Hirano, N.2    Sudo, T.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.