Serial scan test vector compression methodology

Proceedings of the International Test Conference

Volumn , Issue , 1993, Pages 981-988

  Su, Chauchin ^a   Hwang, Kychin ^a  

^a NATIONAL CENTRAL UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DIGITAL INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; STATISTICAL TESTS; VECTORS; VLSI CIRCUITS;

CONSECUTIVE VECTORS; SERIAL SCAN TEST VECTOR COMPRESSION METHODOLOGY; TEST TIME REDUCTION; TEST VECTOR ORDERING ALGORITHMS;

INTEGRATED CIRCUIT TESTING;

EID: 0027883903     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)