Fast timing analysis for hardware-software co-synthesis

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1993, Pages 452-457

  Ye, W ^a   Ernst, R ^a   Benner, Th ^a   Henkel, J ^a  

^a TECHNICAL UNIVERSITY OF BRAUNSCHWEIG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SOFTWARE; CONSTRAINT THEORY; ELECTRIC NETWORK SYNTHESIS; ITERATIVE METHODS; MATHEMATICAL MODELS;

EMBEDDED SYSTEMS; HARDWARE-SOFTWARE COSYNTHESIS; ITERATION LOOP; RUN TIME ANALYSIS;

COMPUTER AIDED NETWORK ANALYSIS;

EID: 0027883326     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (22)