A Physical Poly-Silicon Thin Film Transistors Model for Circuit Simulations

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1993, Pages 497-500

  Li, Chester C ^a   Ikeda, Hiroyuki ^b   Inoue, Takahide ^b   Ko, Ping K ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DRAIN CURRENT; POLYCRYSTALLINE MATERIALS; POLYSILICON; SPICE; THIN FILM CIRCUITS; THIN FILM TRANSISTORS; THIN FILMS; FIELD EFFECT TRANSISTORS; HOT CARRIERS; LIQUID CRYSTAL DISPLAYS; MATHEMATICAL MODELS; MOSFET DEVICES;

CAPACITANCE MODELLING; CHANNEL LENGTH MODULATION; DRAIN-CURRENT MODELING; DRAIN-INDUCED BARRIER LOWERING; GATE INDUCED DRAIN LEAKAGES; HOT-CARRIERS; POLY SILICON; SILICON THIN FILM TRANSISTORS; THIN-FILM TRANSISTOR MODEL;

TIMING CIRCUITS; THIN FILM CIRCUITS;

CHANNEL LENGTH MODULATION (CLM); DRAIN INDUCED BARRIER LOWERING (DIBL); POLY SILICON;

EID: 0027880069     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. J. Levinson, et al, J. Appl. Phys, Feb. 1982, p. 1193
2. J. H. Huang, et al, IEDM Technical Digest, 1992, p. 569
3. T. Y. Chan, et al, IEDM Technical Digest, 1987, p. 718