CELL TECHNOLOGY DIRECTIONS FOR ADVANCED MPUs AND OTHER MEMORY-EMBEDDED LOGIC DEVICES

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1993, Pages 37-40

  Kinugawa, M ^a   Kakumu, M ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CELLS; CMOS INTEGRATED CIRCUITS; COMPUTER CIRCUITS; CYTOLOGY; DYNAMIC RANDOM ACCESS STORAGE; MEMORY ARCHITECTURE; STATIC RANDOM ACCESS STORAGE; STRUCTURAL OPTIMIZATION; CELLULAR ARRAYS; DATA PROCESSING; LOGIC DEVICES; RANDOM ACCESS STORAGE;

ADVANCED-LOGIC DEVICE; CELL TECHNOLOGY; CELL-BE; CELL/B.E; CELL/BE; EMBEDDED MEMORY; MEMORY STRUCTURE; POWER SUPPLY VOLTAGE; TRANSISTOR DESIGNS; VOLTAGE CONDITIONS;

LOGIC DEVICES; DATA STORAGE EQUIPMENT;

CACHE MEMORIES; MEMORY EMBEDDED LOGIC DEVICES; PROCESS COMPATIBILITY;

EID: 0027879112     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. 2, New Poly-Si PMOS Load (PPL) SRAM Cell Having Excellent Soft Error Immunity", IEDM Tech. Dig., pp.48, 1988
2. M. Kinugawa et al, "TFT (Thin Film Transistor) Cell Technology for 4Mbit and More High Density SRAMs", Proc. of Symp. on VLSI Tech., pp.23, 1990