Electrothermal Simulation of Electrical Overstress in Advanced nMOS ESD I/O Protection Devices

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1993, Pages 899-902

  Diaz, Carlos H ^a   Duvvury, Charvaka ^b   Kang, Sung Mo ^c  

^a HEWLETT PACKARD COMPANY   (United States)

^b TEXAS INSTRUMENTS   (United States)

^c UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT SIMULATION; BIPOLAR TRANSISTORS; ELECTRIC PROPERTIES; INTEGRATED CIRCUITS; SEMICONDUCTOR DEVICES; SIMULATION;

CIRCUIT LEVELS; CIRCUIT-LEVEL SIMULATION; DESIGN INPUT; ELECTRICAL OVERSTRESS; ELECTRO-THERMAL SIMULATION; HIGH CURRENT STRESS; INPUT-OUTPUT; PROTECTION DEVICE; SECOND BREAKDOWN; SUBMICRON;

ELECTROSTATIC DEVICES; MOS DEVICES;

ELECTRICAL OVERSTRESS (EOS); ELECTROSTATIC DISCHARGE (ESD); ELECTROTHERMAL SIMULATION;

EID: 0027878006     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

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