A 230-MHz Half-Bit Level Pipelined Multiplier Using True Single-Phase Clocking

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 1, Issue 4, 1993, Pages 415-422

  Somasekhar, Dinesh ^a   Visvanathan, V ^a  

^a INDIAN INSTITUTE OF SCIENCE   (India)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; DIGITAL SIGNAL PROCESSING; MICROPROCESSOR CHIPS; MULTIPLYING CIRCUITS; PIPELINE PROCESSING SYSTEMS;

LATENCY; TRUE SINGLE PHASE CLOCKING;

FREQUENCY MULTIPLYING CIRCUITS;

EID: 0027874716     PISSN: 10638210     EISSN: 15579999     Source Type: Journal    
DOI: 10.1109/92.250188     Document Type: Article

References (20)

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