SCOPUS 정보 검색 플랫폼

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1993, Pages 471-474

Improving gate oxide integrity in p+pMOSFET by using large grain size polysilicon gate

(4) Koda, Munetaka a Shida, Yoshikatsu a Kawaguchi, Junichi a Kaneko, Yoshio a

a JFE STEEL CORPORATION (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BORON; GATES (TRANSISTOR); GRAIN SIZE AND SHAPE; MOS DEVICES; POLYCRYSTALLINE MATERIALS; LSI CIRCUITS;

ELECTRICAL CHARACTERISTIC; GATE OXIDE INTEGRITY; GATE OXIDE QUALITY; GRAINSIZE; LARGEST GRAIN SIZES; PMOS DEVICES; PMOSFET; POLYSILICON GATES; POLYSILICON GRAIN SIZE; TIME USE;

POLYSILICON; MOSFET DEVICES;

ELECTRICAL CHARACTERISTICS; GATE OXIDE INTEGRITY; POLYSILICON GATE;

EID: 0027867599 PISSN: 01631918 EISSN: None Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper

Times cited : (10)

References (7)

1
- 0022027064
- Design tradeoffs between surface and buried-channel FETs
- G. Hu and R. Bruce, "Design tradeoffs between surface and buried-channel FETs", IEEE Trans. Electron Devices, vol. ED-32, p. 584, 1985
- (1985) IEEE Trans. Electron Devices , vol.ED-32 , pp. 584
- Hu, G.¹ Bruce, R.²

2
- 4243132732
- A high performance 0.25μm CMOS technology
- B. Davari et al., "A high performance 0.25μm CMOS technology", IEDM Technical Digest, p. 56, 1988
- (1988) IEDM Technical Digest , pp. 56
- Davari, B.¹

3
- 0024170834
- Doping of n+ and p+ polysilicon in a dual-gate CMOS process
- C. Y. Wong, J. Y.-C. Sun, Y. Taur, C. S. Oh, R. Angelucci. and B. Davari", Doping of n+ and p+ polysilicon in a dual-gate CMOS process", MEDM Technical Digest, p. 238, 1988
- (1988) MEDM Technical Digest , pp. 238
- Wong, C.Y.¹ Sun, J.Y.-C.² Taur, Y.³ Oh, C.S.⁴ Angelucci, R.⁵ Davari, B.⁶

4
- 34250903102
- Anomalous CV characteristics of implanted poly MOS structure in n+/p+ dual gate CMOS technology
- Chih, Y. Lu, J. M. Sung, Howard C. Kirsch, Steven J. Hillenius, T. E. Smith, and Lalita Manchanda, "Anomalous CV characteristics of implanted poly MOS structure in n+/p+ dual gate CMOS technology, "IEEE Electron Device Letters, vol. 10. p. 192, 1989
- (1989) IEEE Electron Device Letters , vol.10 , pp. 192
- Chih, Y.L.¹ Sung, J.M.² Kirsch, H.C.³ Hillenius, S.J.⁴ Smith, T.E.⁵ Manchanda, L.⁶

5
- 85126777154
- 12a-E-9
- M. Kawata and T. Katoda; The 52nd Annual Meeting of Japan Soc. of Applied Physics, 12a-E-9, 1991
- (1991) The 52nd Annual Meeting of Japan Soc. of Applied Physics
- Kawata, M.¹ Katoda, T.²

6
- 0024920290
- The influence of fluorine on threshold voltage instabilities in p+polysilicon gated p-channel MOSFETs
- F. K. Baker et al., "The influence of fluorine on threshold voltage instabilities in p+polysilicon gated p-channel MOSFETs", IEDM Technical Digest, P.443, 1989
- (1989) IEDM Technical Digest , pp. 443
- Baker, F.K.¹

7
- 0025591291
- The effect of silicon gate microstructure and gate oxide process on threshold voltage instabilities in BF2 implanted p+gate p-channel MOSFETs
- Hsing-Huang Tseng, Philip J. Tobin, Frank K. Baker, James R. Pfiester, Keenan Evans, Peter Fejes. "The effect of silicon gate microstructure and gate oxide process on threshold voltage instabilities in BF2 implanted p+gate p-channel MOSFETs", Symposium on VLSI Technology, p. 111, 1990
- (1990) Symposium on VLSI Technology , pp. 111
- Tseng, H.¹ Tobin, P.J.² Baker, F.K.³ Pfiester, J.R.⁴ Evans, K.⁵ Fejes, P.⁶

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.