A 10-b, 75-MHz Two-Stage Pipelined Bipolar A/D converter

IEEE Journal of Solid-State Circuits

Volumn 28, Issue 12, 1993, Pages 1187-1199

  Colleran, William T ^a   Abidi, A A ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; HIGH DEFINITION TELEVISION; INTEGRATED CIRCUITS;

CHIP DISSIPATION; QUANTIZERS; SUBRANGING;

DIGITAL SIGNAL PROCESSING;

EID: 0027867460     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.261991     Document Type: Article

References (20)

1. J. R. Gray and S. C. Kitsopoulos. “A precision sample and hold circuit with subnanosecond switching,” IEEE Trans. Circuit Theory, pp. 389–396, Sept. 1964.
2. K. Poulton, J. J. Corcoran, and T. Hornak. “A 1 GHz 6-bit ADC system,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 962–970, Dec. 1987.
3. A. G. F. Dingwall and V. Zazzu, “An 8 MHz CMOS subranging 8-bit A/D converter,” IEEE J. Solid-State Circuits, vol. SC-20, pp. 1138–1143, Dec. 1985.
4. R. E. J. van de Grift and M. van der Veen, “An 8b 50 MHz video ADC with folding and interpolation techniques,” in ISSCC Dig. Tech. Papers, 1987, pp. 94–95.
5. D. C. Rollenhagen, “High speed A/D converters for radar applications,” in Proc. ISCAS, Munich, Germany, pp. 579–582, 1976.
6. S. H. Lewis and P. R. Gray, “A pipelined 5 MS/s 9-bit analog to digital converter,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 954–961, Dec. 1987.
7. R. Petschacher et al., “A 10-b 75 MSPS subranging A/D converter with integrated sample and hold,” IEEE J. Solid-State Circuits, vol. 25, pp. 1339–1346, Dec. 1990.
8. C. Lane, “A 10-bit 60-MSPS flash ADC,” in Bipolar Circuits and Technology Meeting Dig. Tech. Papers, Minneapolis, MN, pp. 44–47, Sept. 1989.
9. C. S. G. Conroy, W. A. Lane, and M. A. Moran, “Statistical design techniques for D/A conveners,” IEEE J. Solid-State Circuits, vol. 24, pp. 1118–1128, Aug. 1989.
10. P. Vorenkamp and J. P. M. Verdaasdonk, “A 10b 50MS/s pipelined ADC,” in ISSCC Dig. Tech. Papers, San Francisco, CA, pp. 32–33, 1992.
11. R. J. van de Plassche and R. E. J. van de Grift, “A high-speed 7-b A/D converter,” IEEE J. Solid-State Circuits, vol. SC-14, pp. 938–943, Dec. 1979.
12. B. Gilbert, “A monolithic microsystem for analog synthesis of trigonometric functions and their inverses,” IEEE J. Solid-State Circuits, vol. SC-17, pp. 1179–1191, Dec. 1982.
13. A. Arbel and R. Kurz, “Fast analog-digital converter,” IEEE Trans. Nucl. Sci., vol. NS-22, pp. 446–449, Feb. 1975.
14. U. Fiedler and D. Seitzer, “A high-speed 8-b A/D converter based on a Gray code multiple folding circuit,” IEEE J. Solid-State Circuits, vol. SC-14, pp. 547–551, June 1979.
15. J. V. Woods and R. N. Zobel, “Fast synthesized cyclic parallel analog digital converter,” IEEE Proceedings, vol. 127, pp. 45–51, Apr. 1980.
16. R. J. van de Plassche and P. Baltus, “An 8-b 100-MHz full nyquist analog to digital converter,” IEEE J. Solid-State Circuits, vol. 23, pp. 1334–1344, Dec. 1988.
17. C. Mangelsdorf et al., “A two-residue architecture for multistage ADC’s,” in ISSCC Dig. Tech. Papers, San Francisco, CA, pp. 64–65, 1993.
18. J. J. Corcoran et al., “A 400 MHz 6b ADC,” in ISSCC Dig. Tech. Papers, San Francisco, CA, pp. 294–295, 1984.
19. T. Wakimoto, Y. Akazawa, and S. Konaka, “Si bipolar 2 GS/s 6b flash A/D conversion LSI,” in ISSCC Dig. Tech. Papers, San Francisco, CA, pp. 232–233, 1988.
20. J. van Valburg and R. van de Plassche, “An 8b 650MHz folding ADC,” in ISSCC Dig. Tech. Papers, San Francisco, CA, pp. 30–31, 1992.