Latch-Up Performance of a Sub-0.5 Micron Inter-Well Deep Trench Technology

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1993, Pages 731-734

  Gilbert, Percy V ^a   Crabtree, Phil E ^a   Sun, Shih Wei ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

2D SIMULATIONS; BULK CMOS; CMOS TECHNOLOGY; CURRENT CONFINEMENT; DEEP TRENCH STRUCTURE; DEEP TRENCH TECHNOLOGIES; HOLDING VOLTAGE; LATCH-UPS; PERFORMANCE; TRENCH SIDEWALLS;

CMOS INTEGRATED CIRCUITS;

DIFFUSION; LEAKAGE CURRENTS; SIMULATION; SUBSTRATES; TRANSISTORS;

DEEP TRENCH TECHNOLOGY; LATCH UP PERFORMANCE; SIDEWALL INVERSION;

EID: 0027855194     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. R.R. Troutman, “Latch-Up in CMOS Technology”, Kluwer Academic Press, Boston, 1986.
2. K. M. Cham, et. al.,”Characterization and Modeling of the Trench Surface Inversion Problem for the Trench Isolated CMOS Technology”, lEDM Technical Digest, Abstract 2.2, p. 23,1983
3. R. D. Rung, et. al., “Deep Trench Isolated CMOS Devices”, IEDM Technical Digest, Abstract 9.6, p. 237, 1982
4. S. Sun, et. al., “A 0.4 Micron Fully Complementary BiCMOS Technology for Advanced Logic and Microprocessor Applications”, IEDM Technical Digest, Abstract 4.1.1, p. 85,1991.
5. S. Bhattacharya, et. al., “Parametric Study of Latchup Immunity of Deep Trench-Isolated, Bulk, Nonepitaxial CMOS”, IEEE Trans. Electron Devices, Vol. ED-39, p. 921, 1992.
6. R. Rung,”Trench Isolation for Application in CMOS VLSI”,IEDM Technical Digest, Abstract 26.1, p. 574,1984.