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Volumn , Issue , 1993, Pages 236-239
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Design methodology of bipolar standard cell LSIs for Gbit/s signal processing
a
a
NTT CORPORATION
(Japan)
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Author keywords
[No Author keywords available]
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Indexed keywords
COMPUTER AIDED DESIGN;
ELECTRIC LOADS;
ELECTRIC NETWORK ANALYSIS;
EMITTER COUPLED LOGIC CIRCUITS;
INTEGRATED CIRCUIT LAYOUT;
LOGIC GATES;
LSI CIRCUITS;
SCHEMATIC DIAGRAMS;
SIGNAL PROCESSING;
VOICE/DATA COMMUNICATION SYSTEMS;
CELL LIBRARIES;
SYNCHRONOUS DIGITAL HIERARCHY;
BIPOLAR INTEGRATED CIRCUITS;
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EID: 0027853266
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
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Times cited : (7)
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References (5)
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